MIT Terahertz Integrated Electronics Group

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Jaehong Jung

Jaehong Jung

PhD student

  • Sub-THz molecular clock
  • low-noise frequency synthesis

jung0214@mit.edu

Bio

Jaehong Jung (co-advised by Prof. Anantha Chandrakasan) received the B.S. and M.S. degrees in semiconductor systems engineering from Sungkyunkwan University, Suwon, South Korea, in 2015 and 2017. He is currently pursuing the Ph.D. at MIT EECS. Since 2017 he has been with Samsung Electronics, Hwaseong, focused on high-quality clock generation ICs including PLLs, DLLs, on-chip oscillators, and crystal oscillators for SoC platforms and RF transceivers. His interests include high-speed serial links, clock generation ICs, ultra-low power ICs, and fully synthesized calibration algorithms.

Publications 4

Other publications 21

Co-authored before joining the group, or independent collaborations not involving the Han group.

  • CICC Apr 2026

    A 65nm CMOS-Based Ingestible Capsule for Adaptable and pH-Controlled Electrical Stimulation in GI-Tract

    S. Sharma, M. Fayumy, L. Morgan, M. Say, Y.-G. Park, J. Jung, F. Xue, M. Elbeh, S. Meier, Y. Ramadass, Z. Makhambetova, N. Fabian, B. Laidlaw, K. Ramadi, J. Voldman, G. Traverso, A. P. Chandrakasan

    BibTeX 
    @inproceedings{sharma2026capsule_cicc,
  author    = {S. Sharma and M. Fayumy and L. Morgan and M. Say and Y.-G. Park and J. Jung and F. Xue and M. Elbeh and S. Meier and Y. Ramadass and Z. Makhambetova and N. Fabian and B. Laidlaw and K. Ramadi and J. Voldman and G. Traverso and A. P. Chandrakasan},
  title     = {A 65nm CMOS-Based Ingestible Capsule for Adaptable and pH-Controlled Electrical Stimulation in GI-Tract},
  booktitle = {IEEE Custom Integrated Circuits Conference (CICC)},
  year      = {2026},
  month     = {apr},
  venue     = {CICC},
}

  • JSSC Mar 2026

    A Fully-Integrated Wireless Ingestible CMOS Drug-Delivery Chip with Electrochemical Energy Harvesting and pH-Adaptive MPPT for Personalized Therapeutics

    S.-Y. Yang, D. U. Yildirim, S. Sharma, D. Han, R. Mittal, H. Ellis, J. Jung, E. Lee, Y. Cai, G. Traverso, A. P. Chandrakasan

    Invited

    BibTeX 
    @article{yang2026ingestible_jssc,
  author    = {S.-Y. Yang and D. U. Yildirim and S. Sharma and D. Han and R. Mittal and H. Ellis and J. Jung and E. Lee and Y. Cai and G. Traverso and A. P. Chandrakasan},
  title     = {A Fully-Integrated Wireless Ingestible CMOS Drug-Delivery Chip with Electrochemical Energy Harvesting and pH-Adaptive MPPT for Personalized Therapeutics},
  journal   = {IEEE Journal of Solid-State Circuits},
  year      = {2026},
  month     = {mar},
  volume    = {61},
  number    = {3},
  venue     = {JSSC},
  note      = {Invited},
}

  • APCCAS Oct 2025

    A Non-Invasive Ultrasound-Transmission-Based Thermometry Method for Multi-Layer Deep Tissue Monitoring

    S. Shin, J. Jung, M. Manohara, A. Bahai, A. P. Chandrakasan

    BibTeX 
    @inproceedings{shin2025thermometry_apccas,
  author    = {S. Shin and J. Jung and M. Manohara and A. Bahai and A. P. Chandrakasan},
  title     = {A Non-Invasive Ultrasound-Transmission-Based Thermometry Method for Multi-Layer Deep Tissue Monitoring},
  booktitle = {IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)},
  year      = {2025},
  month     = {oct},
  venue     = {APCCAS},
}

  • ESSERC Sep 2025

    A 33.7% Tx Efficiency Crystal-Less BLE-Compatible Transmitter with Adaptive PA Output Power Calibration for Ingestible Devices

    S. Shin, J. Jung, G. Traverso, A. P. Chandrakasan

    BibTeX 
    @inproceedings{shin2025ble_esserc,
  author    = {S. Shin and J. Jung and G. Traverso and A. P. Chandrakasan},
  title     = {A 33.7\% Tx Efficiency Crystal-Less BLE-Compatible Transmitter with Adaptive PA Output Power Calibration for Ingestible Devices},
  booktitle = {IEEE European Solid-State Electronics Research Conference (ESSERC)},
  year      = {2025},
  month     = {sep},
  venue     = {ESSERC},
}

  • CICC Apr 2025

    A Fully-Integrated Wireless Ingestible Drug Delivery Chip with Electrochemical Energy Harvesting and pH-Based MPPT

    S.-Y. Yang, D. U. Yildirim, S. Sharma, D. Han, R. Mittal, H. Ellis, J. Jung, E. Lee, Y. Cai, G. Traverso, A. P. Chandrakasan

    Best Student Paper Award

    BibTeX 
    @inproceedings{yang2025ingestible_cicc,
  author    = {S.-Y. Yang and D. U. Yildirim and S. Sharma and D. Han and R. Mittal and H. Ellis and J. Jung and E. Lee and Y. Cai and G. Traverso and A. P. Chandrakasan},
  title     = {A Fully-Integrated Wireless Ingestible Drug Delivery Chip with Electrochemical Energy Harvesting and pH-Based MPPT},
  booktitle = {IEEE Custom Integrated Circuits Conference (CICC)},
  year      = {2025},
  month     = {apr},
  venue     = {CICC},
  note      = {Best Student Paper Award},
}

  • A-SSCC Nov 2024

    A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module

    J. Kim, J. Jung, K. Lee, B. Sung, J. Kim, B. Lim, T.-G. Noh, J. Lee, H. Seok, Y. Cho, G. Kim, T. Nomiyama, S. Kang, Y. Jeong, S. Cho, G. Kim, D.-H. Oh, J. Kim, Y. Lim, S. Kim, S. Oh, J. Lee

    J. Kim and J. Jung contributed equally.

    BibTeX 
    @inproceedings{kim2024ddr5rcd_asscc,
  author    = {J. Kim and J. Jung and K. Lee and B. Sung and J. Kim and B. Lim and T.-G. Noh and J. Lee and H. Seok and Y. Cho and G. Kim and T. Nomiyama and S. Kang and Y. Jeong and S. Cho and G. Kim and D.-H. Oh and J. Kim and Y. Lim and S. Kim and S. Oh and J. Lee},
  title     = {A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module},
  booktitle = {IEEE Asian Solid-State Circuits Conference (A-SSCC)},
  year      = {2024},
  month     = {nov},
  venue     = {A-SSCC},
  note      = {J. Kim and J. Jung contributed equally.},
}

  • JSSC Jun 2024

    A Fully-Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS

    J. Jung, S. Oh, J. Kim, J. Lee, W. Kim, E. Park, S. Bae, S. Kim, J. Lee, Y. Yoon, Y. Jeong, S.-S. Park, K. Lee, Y. Lim, J. Huh, J. Lee

    BibTeX 
    @article{jung2024cmic_jssc,
  author    = {J. Jung and S. Oh and J. Kim and J. Lee and W. Kim and E. Park and S. Bae and S. Kim and J. Lee and Y. Yoon and Y. Jeong and S.-S. Park and K. Lee and Y. Lim and J. Huh and J. Lee},
  title     = {A Fully-Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS},
  journal   = {IEEE Journal of Solid-State Circuits},
  year      = {2024},
  month     = {jun},
  volume    = {59},
  number    = {6},
  venue     = {JSSC},
}

  • A-SSCC Nov 2023

    A Wide Frequency Range, Small Area, and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3nm Gate-All-Around CMOS

    K. Lee, J. Jung, G. Kim, J. Kim, S. Kim, S. Oh, S.-M. Park, J. Lee

    BibTeX 
    @inproceedings{lee2023gaapll_asscc,
  author    = {K. Lee and J. Jung and G. Kim and J. Kim and S. Kim and S. Oh and S.-M. Park and J. Lee},
  title     = {A Wide Frequency Range, Small Area, and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3nm Gate-All-Around CMOS},
  booktitle = {IEEE Asian Solid-State Circuits Conference (A-SSCC)},
  year      = {2023},
  month     = {nov},
  venue     = {A-SSCC},
}

  • TCAS-II Aug 2023

    A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in a 4nm FinFET CMOS

    K. Lee, J. Jung, S. Kim, S. Oh, J. Lee, S.-M. Park

    BibTeX 
    @article{lee2023quadrupler_tcas2,
  author    = {K. Lee and J. Jung and S. Kim and S. Oh and J. Lee and S.-M. Park},
  title     = {A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in a 4nm FinFET CMOS},
  journal   = {IEEE Transactions on Circuits and Systems II: Express Briefs},
  year      = {2023},
  month     = {aug},
  volume    = {70},
  number    = {8},
  venue     = {TCAS-II},
}

  • VLSI Jun 2023

    A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS

    J. Jung, K. Lee, G. Kong, B. Lim, S. Kim, S. Oh, J. Lee

    BibTeX 
    @inproceedings{jung2023ringpll_vlsi,
  author    = {J. Jung and K. Lee and G. Kong and B. Lim and S. Kim and S. Oh and J. Lee},
  title     = {A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS},
  booktitle = {IEEE Symposium on VLSI Circuits},
  year      = {2023},
  month     = {jun},
  venue     = {VLSI},
}

  • ISSCC Feb 2022

    A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOS

    J. Jung, S. Kim, W. Kim, J. Han, E. Park, S. Hwang, S. Oh, S. Han, K. Lee, J. Huh, J. Lee

    BibTeX 
    @inproceedings{jung2022dcxo_isscc,
  author    = {J. Jung and S. Kim and W. Kim and J. Han and E. Park and S. Hwang and S. Oh and S. Han and K. Lee and J. Huh and J. Lee},
  title     = {A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOS},
  booktitle = {IEEE International Solid-State Circuits Conference (ISSCC)},
  year      = {2022},
  month     = {feb},
  venue     = {ISSCC},
}

  • ISSCC Feb 2022

    A Single-Crystal-Oscillator-Based Clock Management IC with 18x Start-Up Time Reduction and 0.68ppm/°C Duty-Cycled Machine-Learning-Based RCO Calibration

    J. Jung, S. Oh, J. Kim, G. Ha, J. Lee, S. Kim, E. Park, J. Lee, Y. Yoon, S. Bae, W. Kim, Y. Lim, K. Lee, J. Huh, J. Lee, T.-B. Cho

    Anantha P. Chandrakasan Award for Outstanding Distinguished-Technical Paper

    BibTeX 
    @inproceedings{jung2022cmic_isscc,
  author    = {J. Jung and S. Oh and J. Kim and G. Ha and J. Lee and S. Kim and E. Park and J. Lee and Y. Yoon and S. Bae and W. Kim and Y. Lim and K. Lee and J. Huh and J. Lee and T.-B. Cho},
  title     = {A Single-Crystal-Oscillator-Based Clock Management IC with 18x Start-Up Time Reduction and 0.68ppm/°C Duty-Cycled Machine-Learning-Based RCO Calibration},
  booktitle = {IEEE International Solid-State Circuits Conference (ISSCC)},
  year      = {2022},
  month     = {feb},
  venue     = {ISSCC},
  note      = {Anantha P. Chandrakasan Award for Outstanding Distinguished-Technical Paper},
}

  • VLSI Jun 2020

    A 4GHz 0.73ps rms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC

    J. Jung, S. Jung, K. Lee, J. Jung, S. Kim, B. Han, S. Oh, J. Lee

    BibTeX 
    @inproceedings{jung2020sspll_vlsi,
  author    = {J. Jung and S. Jung and K. Lee and J. Jung and S. Kim and B. Han and S. Oh and J. Lee},
  title     = {A 4GHz 0.73ps rms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC},
  booktitle = {IEEE Symposium on VLSI Circuits},
  year      = {2020},
  month     = {jun},
  venue     = {VLSI},
}

  • VLSI Jun 2020

    An RF Transceiver with Fully Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS

    S. Han, J. Jang, J. Lee, D. Jeong, J. Lee, J. Lee, C. Lau, J. Han, S. Lee, J. Bae, I. Cho, S.-Y. Lee, S. Kim, J. Lee, Y. Lee, J. Jung, J. Huh, J. Lee, T.-B. Cho, I. Kang

    BibTeX 
    @inproceedings{han2020nr_vlsi,
  author    = {S. Han and J. Jang and J. Lee and D. Jeong and J. Lee and J. Lee and C. Lau and J. Han and S. Lee and J. Bae and I. Cho and S.-Y. Lee and S. Kim and J. Lee and Y. Lee and J. Jung and J. Huh and J. Lee and T.-B. Cho and I. Kang},
  title     = {An RF Transceiver with Fully Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS},
  booktitle = {IEEE Symposium on VLSI Circuits},
  year      = {2020},
  month     = {jun},
  venue     = {VLSI},
}

  • A-SSCC Nov 2019

    A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS

    B. Sung, C. Lo, J. Lee, S. Jung, S. Kim, J. Jung, S. Bae, Y. Cho, Y. Lim, D. Choi, M. Shin, S. Choi, B. Han, S. Oh, J. Lee

    BibTeX 
    @inproceedings{sung2019rx_asscc,
  author    = {B. Sung and C. Lo and J. Lee and S. Jung and S. Kim and J. Jung and S. Bae and Y. Cho and Y. Lim and D. Choi and M. Shin and S. Choi and B. Han and S. Oh and J. Lee},
  title     = {A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS},
  booktitle = {IEEE Asian Solid-State Circuits Conference (A-SSCC)},
  year      = {2019},
  month     = {nov},
  venue     = {A-SSCC},
}

  • A-SSCC Nov 2019

    A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology

    S. Jung, J. Jung, B. Han, S. Oh, J. Lee

    BibTeX 
    @inproceedings{jung2019ringpll_asscc,
  author    = {S. Jung and J. Jung and B. Han and S. Oh and J. Lee},
  title     = {A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology},
  booktitle = {IEEE Asian Solid-State Circuits Conference (A-SSCC)},
  year      = {2019},
  month     = {nov},
  venue     = {A-SSCC},
}

  • JSSC Oct 2018

    A 0.75–3.0Gb/s Dual-Mode Temperature-Tolerant Reference-Less CDR with a Deadzone-Compensated Frequency Detector

    J. Jin, X. Jin, J. Jung, K. Kwon, J. Kim, J.-H. Chun

    BibTeX 
    @article{jin2018cdr_jssc,
  author    = {J. Jin and X. Jin and J. Jung and K. Kwon and J. Kim and J.-H. Chun},
  title     = {A 0.75–3.0Gb/s Dual-Mode Temperature-Tolerant Reference-Less CDR with a Deadzone-Compensated Frequency Detector},
  journal   = {IEEE Journal of Solid-State Circuits},
  year      = {2018},
  month     = {oct},
  volume    = {53},
  number    = {10},
  venue     = {JSSC},
}

  • JSSC Aug 2018

    A 1.08-nW/kHz 13.2-ppm/°C Self-Biased Timer Using Temperature-Insensitive Resistive Current

    J. Jung, I.-H. Kim, S.-J. Kim, Y. Lee, J.-H. Chun

    BibTeX 
    @article{jung2018timer_jssc,
  author    = {J. Jung and I.-H. Kim and S.-J. Kim and Y. Lee and J.-H. Chun},
  title     = {A 1.08-nW/kHz 13.2-ppm/°C Self-Biased Timer Using Temperature-Insensitive Resistive Current},
  journal   = {IEEE Journal of Solid-State Circuits},
  year      = {2018},
  month     = {aug},
  volume    = {53},
  number    = {8},
  venue     = {JSSC},
}

  • ISSCC SRP Feb 2018

    A 750-Mb/s to 3-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR with a Deadzone-Compensated Frequency Detector

    J. Jin, X. Jin, J. Jung, K. Kwon, J.-H. Chun

    BibTeX 
    @inproceedings{jin2018cdr_isscc_srp,
  author    = {J. Jin and X. Jin and J. Jung and K. Kwon and J.-H. Chun},
  title     = {A 750-Mb/s to 3-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR with a Deadzone-Compensated Frequency Detector},
  booktitle = {IEEE International Solid-State Circuits Conference (ISSCC), Student Research Preview},
  year      = {2018},
  month     = {feb},
  venue     = {ISSCC SRP},
}

  • ISCAS May 2017

    A 17.5-Gb/s Transceiver with a MaxEye-Based Autonomous Adaptation

    J. Jin, X. Jin, S.-H. Kim, I.-H. Kim, J. Jung, K. Kwon, J.-H. Chun

    BibTeX 
    @inproceedings{jin2017transceiver_iscas,
  author    = {J. Jin and X. Jin and S.-H. Kim and I.-H. Kim and J. Jung and K. Kwon and J.-H. Chun},
  title     = {A 17.5-Gb/s Transceiver with a MaxEye-Based Autonomous Adaptation},
  booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
  year      = {2017},
  month     = {may},
  venue     = {ISCAS},
}

  • ICCE-Asia Oct 2016

    An On-Chip Jitter Tolerance Test Circuit for Mobile and Video Interfaces

    I.-H. Kim, J. Jung, S.-H. Kim, J.-H. Chun

    BibTeX 
    @inproceedings{kim2016jtol_iccease,
  author    = {I.-H. Kim and J. Jung and S.-H. Kim and J.-H. Chun},
  title     = {An On-Chip Jitter Tolerance Test Circuit for Mobile and Video Interfaces},
  booktitle = {IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)},
  year      = {2016},
  month     = {oct},
  venue     = {ICCE-Asia},
}