Bio
Jaehong Jung (co-advised by Prof. Anantha Chandrakasan) received the B.S. and M.S. degrees in semiconductor systems engineering from Sungkyunkwan University, Suwon, South Korea, in 2015 and 2017. He is currently pursuing the Ph.D. at MIT EECS. Since 2017 he has been with Samsung Electronics, Hwaseong, focused on high-quality clock generation ICs including PLLs, DLLs, on-chip oscillators, and crystal oscillators for SoC platforms and RF transceivers. His interests include high-speed serial links, clock generation ICs, ultra-low power ICs, and fully synthesized calibration algorithms.
Publications 4
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A 55.8-to-64.2GHz, 58.3fsrms-Jitter, -250.2dB-FoMJ Fractional-N Cascaded PLL in 28nm CMOS
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Self-Programmable Twin PUFs via Photovoltaic Energy Harvesting During the Pre-Wafer-Dicing Stage
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A Fully Integrated 263-GHz Retro-Backscatter Circuit with 105° Reading Angle and 12-dB Conversion Loss
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A 55.8-to-64.2GHz, 58.3fsrms-Jitter, -250.2dB-FoMJ Fractional-N Cascaded PLL in 28nm CMOS